The feature sizes of transistors in CMOS technology continue to shrink as technology advances. As a result, the core supply voltage of integrated circuits also drops. For example, when feature sizes shrink from 0.15 nm technology to 90 nm technology, the core supply voltage drops to 0.9V from 1.5V. However, when interfacing the integrated circuit with external components, in many cases the integrated circuit needs to be compatible with older technologies having a 3.3V supply.
Generally a field programmable gate array (FPGA) operates using different voltages for the logic inside the chip. For example, core logic can be operated at a voltage of 1V while the pre-driver circuits for the input/output (I/O) circuits can be operated at a voltage of 1.8 v. The only restriction is typically that the output voltage that the FPGA sends to off-chip devices to which it is coupled should be as per a standard for those external devices.
VCCO is a general term used for output stage power supply voltage. There is no fixed level for the VCCO supply for an FPGA, but the range is typically from 1.2V to 3.6V. This voltage value is determined by interface specifications for the protocol between the FPGA and the other integrated circuit (IC) devices communicating with the FPGA. If the FPGA is programmed to the LVCMOS25 standard, it is expected that the FPGA and the ICs communicating with the FPGA operate using an output stage voltage (VCCO) of 2.5V. If the FPGA is programmed to the DDR3 standard, it is expected that the FPGA and the DDR3 IC communicating with the FPGA operate using an output stage voltage (VCCO) of 1.5V. If the FPGA is programmed to the DDR4 standard, it is expected that FPGA and the DDR4 communicating with the FPGA operate using an output stage voltage (VCCO) of 1.2V. Ideally, an FPGA should be able to interface with other ICs at any voltage within this range.
Generally the power supply voltage for the internal logic in an FPGA is 1V to operate the transistors at their maximum speed. When this internal voltage is driving the final stage (driver), the driver transistor will see the internal voltage on its gate, but will see the external voltage VCCO across its source/drain terminals (e.g., 1.5V).
Some integrated circuit manufacturing processes that are used to fabricate FPGA ICs support oxide thicknesses that allow operating voltages of 2.5V for CMOS I/O transistors and 1V for CMOS core transistors. As briefly noted above, the manufactured FPGA has to support various standards with variety of voltages, ranging from 1.2V to 3.3V. However, when used to implement DDR3 and DDR4 interfaces, a 2.5V I/O transistor operating at voltages of 1.5V and 1.2V cannot perform at the targeted DDR3 and DDR4 speeds.
There are several reasons for this deficiency. Due to its thick oxide, the 2.5V I/O transistor is slow and exhibits a threshold voltage, commonly expressed as Vth, of 800 mv. With a Vth of 800 mV and lower output voltages (1.5V and 1.2V) of the respective DDR3 and DDR4 interfaces, the gate-source overdrive voltage (head room) is so low that the transistors cannot switch at higher speeds. If output transistors are sized larger to achieve the higher switching speeds, their self-capacitance dominates and contributes to limiting the switching speeds.
By optimizing size and speed, a 2.5V I/O transistor can switch at maximum speed of 333 MHz with output voltages compatible with DDR3 and DDR4, however minimum speeds for DDR3 and DDR4 are respectively 400 MHz and 800 MHz. Using 1.8V I/O transistors at the output stage to resolve this conflict involves major process changes and multiple oxide implants. This will increase the manufacturing costs, and may not even be possible to do because of the required process modifications.
Previous generations of general-purpose input/output (GPIO) circuits do not have DDR3 capability. A current challenge in GPIO circuits is the need for an internal block design (level shifter/pre-driver) to be able to use 2.5V thick oxide transistors for reliability and yet be capable of DDR3 and DDR4 speeds.
If an FPGA device has to accommodate DDR3 and DDR4 speeds using standard design architectures, it will have to compromise on device reliability and contend with significant process cost increases. If the 1V core transistors are used to implement DDR3 and DDR4 interfaces, requiring operating voltages of 1.5V and 1.2V, these transistors cannot sustain the excess stress and moreover they will prevent the FPGA from interfacing with DDR devices. This will defeat the purpose of using an FPGA in a variety of electronic applications.
The present invention addresses the specific problem of using the FPGA I/O buffers to operate at low operational voltages and high speeds that are necessary to operate DDR3/4 devices. The FPGA I/O buffers preferably do not have problems operating at the lower speeds encountered with interfaces like LVCMOS15/12.
A level shifter circuit is required to convert the signals from the core supply level to the I/O supply level in order to communicate with outside components. The conventional level shifter circuits in the GPIO circuits are targeted for high voltage standards like LVCMOS33/25 PCI. The maximum voltage is 3.6V. The 2.5V device can withstand 3.6V by increasing its length proportionately. A conventional level shifter circuit can fulfill the task of converting a 1.5V signal to a 3.3V signal. However, in 90 nm technology or other technologies that provide a very low core supply voltage, present level shifter circuits can only handle relatively low speed signals. Current GPIO circuits are speed restricted due to use of the extra-long thick oxide devices needed to tolerate up to 3.6V at the output. Advanced techniques are needed to improve the speed and performance at DDR3, DDR4 speeds.